In the field of display technology, a flat panel display device, such as liquid crystal display (LCD) and organic light emitting display (OLED) plays an important role in the field of display technology for its advantages of lightness, thinness, low power consumption, high brightness and high image quality. Especially the flat panel display device with big size, high resolution and high image quality, such as liquid crystal TV, prevails in the current flat panel display device market.
Currently, delay of image signals is one of the key factors that limit progress of the flat panel displaying device with big size, high resolution and high image quality. Delay of image signals is mainly determined by signal resistance R and related capacitance C of gates, gate lines or data lines and the like on the array substrate. As the size of the display device continuously increases and the resolution unceasingly improves, signal frequency applied by a driver circuit also increases, and delay of the images signals gets worse. During displaying an image, gate lines are turned on and the pixels are charged. However, as a result of the delay of images signals, some pixels are insufficiently charged, which makes brightness of the picture non-uniform, and thus the display quality of images is affected badly. Lowering resistance of gates, gate lines and data lines etc. can reduce the delay of the image signals and improve image quality.
At present, the method of lowering resistance of gate lines and date lines is: employing metal Cu with lower resistivity to make gate lines and date lines. However, there are following defects:
A buffer layer is required due to poor adhesion of metal Cu to the substrate, and the buffer layer commonly used is made of Ti or Ti alloy. Since Ti is difficult to etch, usually, acid liquid HF is required in the etch process. If the substrate is a glass substrate, acid HF will erode the glass substrate to some degree, deteriorating the performance of the array substrate.
Further more, in prior arts, in the process of making film of each layer of the array substrate, firstly a pattern of a buffer layer is formed through one patterning process such as coating, masking, exposing, developing, photolithographic etching and so on. Subsequently, a pattern of film of each layer of thin film transistor (TFT) is formed on the substrate on which the buffer layer is formed through another patterning process. Since the patterning process is very complicated, the cost of the array substrate is higher.